Integrated circuit with improved channel stress properties and a method for making it
US7045408B2 · kind B2 · utility
14Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Sep 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the silicate glass layer. Also described is a method for forming an integrated circuit. That method comprises forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate, forming a silicate glass layer on only the PMOS transistor structure or the NMOS transistor structure, and forming an etch stop layer on the silicate glass layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.