Formation of finFET using a sidewall epitaxial layer
US7078299B2 · kind B2 · utility
103Cited by
6References
11Claims
0Family size
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Key dates
| Filing date | Sep 3, 2003 |
| Grant date | Jul 18, 2006 |
| Priority date | — |
| Expiry date | Sep 3, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/933
- WIPO fieldMedical technology
- WIPO sectorInstruments
Abstract
A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.