Defect diagnosis for semiconductor integrated circuits

US7089514B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• James W. Adkisson · Jericho, US
• Greg Bazan · South Burlington, US
• John M. Cohn · South Burlington, US
• Francis Gravel · Colchester, US
• Leendert M. Huisman · South Burlington, US
• Phillip J. Nigh · Williston, US
• Leah Pastel · Saint Johnsbury Center, US
• Kenneth Rowe · Burlington, US
• Thomas G. Sopchak · Williston, US
• David E. Sweenor · South Burlington, US

Key dates

• Filing date: Aug 10, 2004
• Grant date: Aug 8, 2006
• Expiry date: Dec 11, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318342
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.