Semiconductor fabrication process including recessed source/drain regions in an SOI wafer

US7091071B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Voon-Yew Thean · Fishkill, US
• Brian J. Goolsby · Austin, US
• Bich-Yen Nguyen · Austin, US
• Thien T. Nguyen · Fremont, US
• Tab A. Stephens · Kyle, US

Key dates

• Filing date: Jan 3, 2005
• Grant date: Aug 15, 2006
• Expiry date: Jan 3, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6727

Abstract

A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.