Dual damascene structure and method

US7091612B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• International Business Machines Corporation · US

Inventors

• Kaushik A. Kumar · Heverlee, BE
• Timothy J. Dalton · Ridgefield, US
• Larry Clevenger · Lagrangeville, US
• Andy Cowley · Wappingers Falls, US
• Douglas C. La Tulipe, Jr. · Albany, US
• Mark Hoinkis · Fishkill, US
• Chih-Chao Yang · Glenmont, US
• Yi-Hsiung Lin · Zhubeikou, TW
• Erdem Kaltalioglu · Newburgh, US
• Markus Naujok · Hopewell Junction, US
• Jochen Schacht · Hsinchu, TW

Key dates

• Filing date: Oct 14, 2003
• Grant date: Aug 15, 2006
• Expiry date: Oct 14, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/12044
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.