Method and system for controlling MRAM write current to reduce power consumption
US7110289B1 · kind B1 · utility
153Cited by
5References
8Claims
0Family size
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Key dates
| Filing date | Mar 31, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Mar 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.