STI formation in semiconductor device including SOI and bulk silicon regions

US7118986B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Michael D. Steigerwalt · Newburgh, US
• Mahender Kumar · Hopewell Junction, US
• Herbert L. Ho · New Windsor, US
• David M. Dobuzinsky · New Windsor, US
• Johnathan E. Faltermeier · San Jose, US
• Denise Pendleton · Wappingers Falls, US

Key dates

• Filing date: Jun 16, 2004
• Grant date: Oct 10, 2006
• Expiry date: Jun 16, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76283
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.