Semiconductor integrated circuit device
US7123535B2 · kind B2 · utility
65Cited by
4References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2004 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Dec 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.