Process for producing and removing a mask layer

US7129173B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Heike Drummer · Neustadt an der Donau, DE
• Franz Kreupl · Mountain View, US
• Annette Sanger · Dresden, DE
• Manfred Engelhardt · Feldkirchen-Westerham, DE
• Bernhard Sell · Dresden, DE
• Peter Thieme · Dresden, DE

Key dates

• Filing date: Aug 27, 2003
• Grant date: Oct 31, 2006
• Expiry date: Mar 4, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/30625
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.