Stabilizing fluorine etching of low-k materials
US7132363B2 · kind B2 · utility
15Cited by
14References
15Claims
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Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Mar 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Damascene processing is implemented with dielectric barrier films (50, 90, 91) for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films (50, 31) to avoid misalignment problems. Embodiments further include dual damascene (100A, 100B) processing using Cu metallization (100).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.