Method for minimizing slip line faults on a semiconductor wafer surface
US7138344B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2003 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Dec 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique. The method includes heating the semiconductor wafer from an ambient temperature to a first higher temperature and pausing the heating at the first higher temperature for a time sufficient to stabilize the wafer. Then the wafer is heated further from the first higher temperature to a target higher temperature during a predetermined time interval. The further heating during an initial portion of the time interval is conducted at a relatively low heating rate and the heating during a final portion of the time interval is conducted at a relatively higher heating rate to thus minimize slip line faults in the surface of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.