Method and structures for reduced parasitic capacitance in integrated circuit metallizations

US7160795B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Shubneesh Batra · Boise, US
• Michael Chaine · Boise, US
• Brent Keeth · Boise, US
• Salman Akram · Boise, US
• Troy A. Manning · Meridian, US
• Brian Johnson · Boise, US
• Chris G. Martin · Boise, US
• Todd A. Merritt · Boise, US
• Eric J. Smith · Boise, US

Key dates

• Filing date: Nov 12, 2002
• Grant date: Jan 9, 2007
• Expiry date: Apr 3, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/30105
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.