Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device

US7163860B1 · kind B1 · utility

Assignee

• Spansion LLC. · US

Inventors

• Tazrien Kamal · Atlanta, US
• Yun Wu · Sunnyvale, US
• Mark T. Ramsbey · Sunnyvale, US
• Jean Y. Yang · Sunnyvale, US
• Arvind Halliyal · Cupertino, US
• Rinji Sugino · San Jose, US
• Hidehiko Shiraiwa · San Jose, US
• Fred Cheung · San Jose, US

Key dates

• Filing date: May 6, 2003
• Grant date: Jan 16, 2007
• Expiry date: Nov 5, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/954

Abstract

The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.