Structure and method for local resistor element in integrated circuit technology

US7166904B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jason P. Gill · Saint Johnsbury Center, US
• Terence B. Hook · Jericho, US
• Randy W. Mann · Jericho, US
• William J. Murphy · North Ferrisburgh, US
• William R. Tonti · South Burlington, US
• Steven H. Voldman · South Burlington, US

Key dates

• Filing date: Feb 3, 2004
• Grant date: Jan 23, 2007
• Expiry date: Feb 3, 2024

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/904

Abstract

A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.