Semiconductor memory having charge trapping memory cells and fabrication method

US7184291B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• Infineon Technologies Flash GmbH & Co. KG · DE

Inventors

• Michael Bollu · Munich, DE
• Armin Kohlhase · Neubiberg, DE
• Christoph Ludwig · Radeberg, DE
• Herbert Palm · Hohenkirchen, DE
• Josef Willer · Riemerling, DE

Key dates

• Filing date: Jun 3, 2005
• Grant date: Feb 27, 2007
• Expiry date: Aug 25, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.