Generation of metal holes by via mutation
US7188321B2 · kind B2 · utility
2Cited by
3References
9Claims
0Family size
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Key dates
| Filing date | Nov 6, 2003 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Jun 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.