Semiconductor memory device and defect remedying method thereof
US7203101B2 · kind B2 · utility
Assignees
Inventors
- Kazuhiko Kajigaya
- Kazuyuki Miyazawa
- Manabu Tsunozaki
- Kazuyoshi Oshima
- Takashi Yamazaki
- Yuji Sakai
- Jiro Sawada
- Yasunori Yamaguchi
- Tetsurou Matsumoto
- Shinji Udo
- Hiroshi Yoshioka
- Hirokazu Saito
- Mitsuhiro Takano
- Makoto Morino
- Sinichi Miyatake
- Eiji Miyamoto
- Yasuhiro Kasama
- Akira Endo
- Ryoichi Hori
- Jun Etoh
- Masashi Horiguchi
- Shinichi Ikenaga
- Atsushi Kumata
Key dates
| Filing date | Jan 12, 2006 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Jan 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.