Semiconductor device with a non-erasable memory and/or a nonvolatile memory
US7206216B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | May 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.