Resistive memory arrangement
US7215568B2 · kind B2 · utility
60Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2005 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Aug 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.