Transistor fabrication using double etch/refill process

US7226820B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Da Zhang · New Taipei, TW
• Jing Liu · Austin, US
• Bich-Yen Nguyen · Austin, US
• Voon-Yew Thean · Fishkill, US
• Ted R. White · Austin, US

Key dates

• Filing date: Apr 7, 2005
• Grant date: Jun 5, 2007
• Expiry date: Feb 8, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.