Self-aligned low-k gate cap
US7230296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2004 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Jan 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10–18%. The inventive CMOS structure includes at least one gate region including a gate conductor located atop a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.