Memory system and method for strobing data, command and address signals
US7245553B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2006 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Feb 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.