System and method for integrating in-situ metrology within a wafer process
US7252097B2 · kind B2 · utility
12Cited by
11References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 24, 2003 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Jan 7, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S134/902
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method for processing a wafer includes applying a process to the wafer. The process being supported by a surface tension gradient device. A result of the process is monitored. The monitored result is output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.