Pitch reduced patterns relative to photolithography features
US7253118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2005 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Aug 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3088
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transfer…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.