Method and apparatus employing integrated metrology for improved dielectric etch efficiency
US7265382B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2002 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Nov 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile and underlying layer thickness measured at several points on the wafer to adjust the next process the inspected wafer will undergo (e.g., the etch process). After the processing step, dimensions of a structure formed by the process, such as the CD and depth of a trench formed by the process, are measured at several points on the wafer, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. In certain embodiments, the CD, profile, thickness and depth measurements, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.