Silicon chip carrier with conductive through-vias and method for fabricating same
US7276787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2003 |
| Grant date | Oct 2, 2007 |
| Priority date | — |
| Expiry date | Jun 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.