Layout modification using multilayer-based constraints
US7284231B2 · kind B2 · utility
12Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2004 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Dec 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.