Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin
US7313769B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2004 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Apr 8, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.