Multiple layer resist scheme implementing etch recipe particular to each layer
US7352064B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2004 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Jul 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.