DRAM memory cell

US7368752B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Richard Luyken · Munich, DE
• Franz Hofmann · Munich, DE
• Lothar Risch · Neubiberg, DE
• Dirk Manger · Dresden, DE
• Wolfgang Rosner · Hersbruck, DE
• Till Schlosser · Dresden, DE
• Michael Specht · Munich, DE

Key dates

• Filing date: May 6, 2004
• Grant date: May 6, 2008
• Expiry date: Nov 1, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6211

Abstract

A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.