Value-based memory coherence support

US7412567B2 · kind B2 · utility

Assignee

• Sun Microsystems Inc. · US

Inventors

• Hakan Zeffer · Stuvsta-Snättringe, SE
• Erik E. Hagersten · Palo Alto, US
• Anders Landin · Redwood City, US
• Shailender Chaudhry · San Francisco, US
• Paul N. Loewenstein · Palo Alto, US
• Robert E. Cypher · Saratoga, US
• Zoran Radovic · Lidingö, SE

Key dates

• Filing date: Apr 28, 2006
• Grant date: Aug 12, 2008
• Expiry date: Oct 18, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/0897
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.