Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US7413979B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2006 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Jul 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the bond-pad being electrically coupled to the integrated circuit. A conductive line is then formed on the die, the conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line, and depositing an electrically conductive material in at least a portion of the passage to form a conductive interconnect extending at least generally through the microelectronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.