Semiconductor fabrication process including silicide stringer removal processing

US7446006B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Dharmesh Jawarani · Round Rock, US
• John R. Alvis · Austin, US
• Michael G. Harrison · Round Rock, US
• Leo Mathew · Austin, US
• John E. Moore · Lutz, US
• Rode R. Mora · Austin, US

Key dates

• Filing date: Sep 14, 2005
• Grant date: Nov 4, 2008
• Expiry date: Jan 27, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/2855
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134). After the etch back the wafer (101) may be dipped in piranha solution and cleaned with an RF sputter (140) of argon.