IC layout optimization to improve yield

US7503020B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Robert J. Allen · South Harwich, US
• Faye D. Baker · Burlington, US
• Albert M. Chu · Nashua, US
• Michael S. Gray · Saint Albans, US
• Jason D. Hibbeler · Williston, US
• Daniel N. Maynard · Craftsbury Common, US
• Mervyn Y. Tan · Colchester, US
• Robert F. Walker · South Burlington, US

Key dates

• Filing date: Jun 19, 2006
• Grant date: Mar 10, 2009
• Expiry date: Jun 22, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/39
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.