Regulating unused/inactive resources in programmable logic devices for static power reduction
US7504854B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2004 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Jul 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17784
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of operating a programmable logic device, including the steps of using a full VDD supply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ VDD) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.