Modified hybrid orientation technology

US7524707B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Olubunmi O. Adetutu · Austin, US
• Mariam Sadaka · Austin, US
• Ted R. White · Austin, US
• Bich-Yen Nguyen · Austin, US

Key dates

• Filing date: Aug 23, 2005
• Grant date: Apr 28, 2009
• Expiry date: Jan 17, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D87/00

Abstract

A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.