Methods and apparatus for designing and using micro-targets in overlay metrology
US7526749B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Oct 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for fabricating a semiconductor die including several target structures. A first layer is formed that includes one or more line or trench structures that extend in a first direction. A second layer is formed that includes one or more line or trench structures that extend in a second direction that is perpendicular to the first structure, such that a projection of the target structure along the first direction is independent of the second direction and a projection of the target structure along the second direction is independent of the first direction. A target structure and a method for generating a calibration curve are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.