Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques
US7541288B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 8, 2007 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Mar 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least one valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.