Method of fabricating semiconductor integrated circuit device
US7553766B2 · kind B2 · utility
1Cited by
21References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 4, 2007 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Dec 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.