Flip chip and wire bond semiconductor package

US7554185B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Chee Seng Foong · Bandar Baru Sungai Buloh, MY
• Aminuddin Ismail · Kapar, MY
• Wai Yew Lo · Petaling Jaya, MY
• Bee Hoon Liau · Kapar, MY
• Jin- Mei Liu · Tianjin, CN
• Jian Wang · Beijing, CN
• Jin Yao · San Diego, US
• Fu-Bin Song · Tianjin, CN

Key dates

• Filing date: Oct 31, 2005
• Grant date: Jun 30, 2009
• Expiry date: Oct 31, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/16152
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor package and method of forming the package, including a substrate having an opening formed therein. Contact pads are formed about a periphery of the opening on a first side of the substrate and a second opposing side of the substrate. A flip chip die is mounted to the substrate, having an active side mounted on a first side of the substrate and in electrical communication with at least some of the contact pads formed on the first side of the substrate. At least one wire bond die is mounted through the opening, with a non-active side mounted on the active side of the flip chip die. The wire bond die is in electrical communication with at least some of the plurality of contact pads formed on the second opposing side of the substrate.