Patent · US Active

Resistive memory arrangement

US7561460B2 · kind B2 · utility

10Cited by

7References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Corvin Liaw · Birkenfeld, DE
Thomas Roehr · Yokohama, JP
Michael Kund · Bad Aibling, DE

Key dates

Filing date	Mar 20, 2007
Grant date	Jul 14, 2009
Priority date	—
Expiry date	Jan 2, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C2213/79
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.