Multi-step barrier deposition method
US7576002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2005 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Nov 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76865
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rather than the target with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls and a second step sputter deposits a second barrier layer, for example of Ta/TaN, onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.