Asymmetric spacers and asymmetric source/drain extension layers
US7585735B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2005 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Feb 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions (162); and/or (d) the device has an oxide layer (160) disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.