System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
US7657864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2007 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Aug 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/705
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.