Atomic layer deposition processes for non-volatile memory devices

US7659158B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Yi Ma · Orlando, US
• Shreyas Kher · Campbell, US
• Khaled Ahmed · Anaheim, US
• Tejal Goyani · Sunnyvale, US
• Maitreyee Mahajani · Saratoga, US
• Jallepally Ravi · Santa Clara, US
• Yi-Chiau Huang · Fremont, US

Key dates

• Filing date: Mar 31, 2008
• Grant date: Feb 9, 2010
• Expiry date: Apr 18, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.