Double-sided integrated circuit chips

US7670927B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kerry Bernstein · Underhill, US
• Timothy J. Dalton · Ridgefield, US
• Jeffrey P. Gambino · Gresham, US
• Mark D. Jaffe · Shelburne, US
• Paul D. Kartschoke · Williston, US
• Stephen E. Luce · Underhill, US
• Anthony K. Stamper · Williston, US

Key dates

• Filing date: May 16, 2006
• Grant date: Mar 2, 2010
• Expiry date: Sep 4, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.