Semiconductor integrated test structures for electron beam inspection of semiconductor wafers
US7679083B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Apr 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.