Patent · US Active

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

US7696052B2 · kind B2 · utility

5Cited by
1References
13Claims
0Family size

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Inventors

Key dates

Filing dateNov 9, 2006
Grant dateApr 13, 2010
Priority date
Expiry dateApr 13, 2027

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/038

Abstract

By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.