False connection for defeating microchip exploitation
US7701244B2 · kind B2 · utility
6Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2008 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Jul 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/32225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.