Method for reducing silicide defects in integrated circuits
US7745320B2 · kind B2 · utility
5Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2008 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | May 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.